HyperLynx 2504: New Features and Improvements
Long-awaited release of HyperLynx 2504 is built with the desire to accelerate electronic design cycles, improve product quality, and help engineering teams find and fix issues earlier in the R&D process. In this article let’s explore what’s new in the latest HyperLynx 2504 release and how each tool from the product family is actually changing.
HyperLynx Signal Integrity and Power Integrity
HyperLynx Analog Mixed Signal (AMS) analysis
HyperLynx Signal Integrity and Power Integrity
Improved Wiring Control in LineSim
Users can now manually adjust wire segments in LineSim to resolve overlaps created by auto-routing. The auto-wiring algorithm has also been improved when exporting from BoardSim to LineSim, giving more control over schematic cleanup and improving simulation accuracy.
Direct Access to Materials Database
The Stackup Editor now offers direct access to the materials database through the File menu. Users can review or edit material properties and filter materials by stackup type, helping with planning and selection without unnecessary clutter.
HyperLynx PI: Enhanced Power Network Setup and Management
The Series and Parallel Components dialog now automatically lists inductors and ferrite beads and includes filtering options based on resistance. Power-supply net candidates can be previewed and updated quickly. Within the Power Network Schematic, users can assign models by clicking on specific nets or components and include or exclude nets from the supply.
HyperLynx PI: Improved Multi-Phase VRM Modeling
A new multi-phase option automatically creates phases and assigns power pins. Resistance values for AC and DC are now separated, with an Rdc field specifically for DC models. Bulk parameter updates are supported, and users can save configurations in a reusable *.hlpimodel file, compatible with single-phase and multi-phase VRMs.
HyperLynx PI: DC Drop Analysis and Power Constraints
DC Drop Interactive and Batch modes can now be launched directly from the Power Network interface. New power constraints include limits on voltage drop and power density at the IC and layer level. The PowerScope Viewer provides a clear DC power density plot, and HTML reports now include detailed voltage and power metrics.
HyperLynx PI: Decoupling Analysis
The HyperPI engine is now integrated into the Decoupling Wizard, offering up to 10X faster simulations for large power nets. It also supports power-aware simulations and capacitor optimization workflows through PDN Extractor and PDN Decoupling Optimizer. Passive component models can be reused across DC and AC domains using IBIS models included in the install directory.
HyperLynx SI: Expanded DDR5 and LPDDR5x Support
Support now includes additional DDR5 speed grades (8000, 8400, and 8800 MT/s) and LPDDR5x at 9600 MT/s. The protocol-aware DDRx Batch Wizard handles configuration automatically. New controls allow for limiting aggressors in IBIS-AMI simulations, with simulation behavior defined when aggressor limits are exceeded.
HyperLynx SI: Simplified Simulation Control
The simulation control page has been redesigned for ease of use. Users can now choose between “Basic” (faster, LTI-based) and “Advanced” (more accurate) IBIS-AMI simulation modes. Address/control and data buses can be configured independently, and key settings like voltage corners and jitter reporting are now centralized.
Eye Diagram Viewer Enhancements
Eye diagrams can now be launched directly from Write and Read tabs in HTML reports, saving time by eliminating the need to search through hundreds of plots. A new Bit Error Rate (BER) column has been added to clarify which bit error rate was used during evaluation for each interface.
Support for PRBS23 in Stimulus Editor
The Stimulus Editor now supports PRBS23, generating sequences over 8 million bits long. This allows for higher accuracy in evaluating eye diagrams and better insight into long-term signal performance.
Repeater Support in IBIS-AMI Flow
HyperLynx now supports repeater models using IBIS 7.2 syntax. The SerDes Batch Wizard allows definition of redrivers and retimers, with repeater support extended into BoardSim and LineSim for export and eye diagram viewing. HTML reports also reflect these updates with data shown at each repeater stage.
New JESD Protocol Classes
Support is added for JESD204 Class B-3, B-6, and B-12, with speed ranges from 312.5 Mbps to 12.5 Gbps. Eye mask enhancements now allow for complex shapes and horizontal shifting to evaluate margin more precisely. Eye contour and bathtub plots are now embedded directly into HTML or PDF reports using lightweight Plotly-based visuals.
Updated Compliance Wizard and Protocol Files
The Compliance Wizard engine now matches COM 4.6 and supports new protocols such as OIF-CEI 224G and IEEE 802.3dj 200G. Configuration files have been updated accordingly, and new documentation is included for SerDes signal integrity compliance.
HyperLyns Advanced Solvers
3D Area Manager Enhancements in BoardSim
The 3D Area Manager now supports importing and exporting 3D area definitions, enabling reuse across designs and simplifying project setup. Users can also set the data folder path directly from the manager screen to ensure project consistency and better file organization.
Each 3D area now displays reference designators and solution status in dedicated columns, making it easier to track progress and area definitions. A new option to automatically select area nets allows users to instantly highlight relevant nets for faster visual analysis.
3D Area Statistics and Quick View Access
Users can now view detailed statistics for selected 3D areas, including overlap detection and area properties, directly within BoardSim. A quick 3D view of any area can be launched from within the BoardSim window, reducing the need to switch to 3D Explorer for basic visualization. For deeper analysis, 3D Explorer remains available.
3D Area GUI Based Connector Pin Placement
A new “Expert Properties” section has been added for users needing compatibility with earlier HyperLynx versions. Parameters such as solder ball diameter, layer thickness, and pin size can now be toggled or edited directly in the 3D Area interface. This ensures older projects remain accessible and editable without requiring conversion.
Advanced Port Options from BoardSim
Users can now modify external ports and reference configurations from the Advanced Port Options dialog within BoardSim. This avoids the need to launch Advanced Solvers separately and provides direct access to previously defined expert parameters for components.
Full-Wave Solver: Small Object Removal
A new command allows users to automatically remove small objects or edges that may interfere with simulation accuracy. The tool provides feedback on the number of objects removed per layer, helping users fine-tune models for better solver performance.
Free Cloud-Based Workshops on Xcelerator Academy
To help users get started and build confidence with HyperLynx tools, Siemens offers free, step-by-step workshops via Xcelerator Academy. These online sessions provide full workflows, practical examples, and guided video instructions. Workshops can be completed without installing HyperLynx locally and are ideal for learning in the cloud or refining skills in advanced simulation techniques.
- DC Drop
- DDR5 Model-free Post layout Verification
- Design Rule Check – DDR4 Based Rules
- PDN Decoupling with AMD Versal FPGA
- DDR4 Power-Aware
- Design Space Exploration – Differential Via Optimization
- PCIe Gen 3 Compliance Verification
- Compliance-based Serial Link Design and Verification
- HyperLynx AMS Parasitic Extraction
HyperLynx DRC
Modern UI Enhancements and Tooling Improvements
HyperLynx DRC now includes a native stackup editor when running on Windows. The modern user interface has been expanded with external automation support and a built-in script debugger. Users may also benefit from added component placement layer visibility and improved support for custom user layers in Xpedition and Allegro workflows.
Smarter Design Handling and Feedback
Designs can now be imported directly from ODB++ folders. A new progress indicator shows the loading status, providing clear feedback as layout data is processed. Reviewing results is more efficient thanks to updates that help toggle directly to related violations in the results window.
Advanced Creepage Analysis and 3D Rule Support
The creepage engine in version 2504 introduces significant updates. Violations are now shown more clearly using cyan, red, and gray paths to visualize net connections, including floating metals and cross-layer routing. The engine now works on partially routed nets and offers better performance. Two new parameters have been added: “Calculate Danger Zones” and “Exclude Constant Nets” for more precise rule control. All features are compatible with both 1 nm and 10 nm database configurations.
New IC Packaging Rules
New IC Packaging Rules
Two new out-of-the-box checks have been added for IC packaging:
- Exposed Vias checks minimum copper clearance when vias are embedded in planes.
- Missing Teardrop checks whether traces extending from vias include the required teardrop when certain length and width conditions apply.
Improved Integration with Allegro
HyperLynx DRC now synchronizes views with Allegro. When a violation is selected in HyperLynx, Allegro automatically displays the matching layer and zooms to the correct location. This allows quick updates within the layout tool. Embedded components are now shown in Allegro’s visibility settings, and tie-bars are automatically treated as series components for better rule processing.
HyperLynx Schematic Analysis
Faster Model Creation from Xpedition Schematics
Users can now automatically generate passive and connector models directly from Xpedition Designer schematics. This option is available in Project Creator dialog under the “Models” tab. It can cover up to 70 percent of the components in a typical design, helping teams start simulations faster.
Direct Import from FPGA I/O Optimizer
FPGA Xchange files exported from IOPT can now be imported directly in the FPGA auto-modeler. This makes it easier to check late-stage pinout changes. Missing voltage data can be quickly filled in using dropdown menus.
Support for Multiple Model Libraries
HyperLynx now supports connections to several model libraries at once. There is no need to switch or merge databases. Users can search across all libraries, set priority by drag and drop, and write to one selected source. Both file-based and server-based libraries are supported.
Improved Review Tracking
A new checklist column in the Results tab helps users track which simulation results have already been reviewed. This makes it easier to continue where you stopped last time and clearly shows progress.
HyperLynx Analog Mixed Signal (AMS) analysis
One-Click Transfer from PartQuest Explore
Designs created in PartQuest Explore can now be imported into HyperLynx AMS in a single step. This reduces setup time, avoids manual errors, and streamlines the workflow. PartQuest Explore is a free, cloud-based design environment based on the same simulator core as HyperLynx AMS. By moving a design to HyperLynx AMS, users gain access to more powerful analysis tools and can move forward to PCB layout using Xpedition Designer.
Support for Verilog-AMS Models
HyperLynx AMS now supports Verilog-AMS, a hardware description language that handles both analog and digital functionality. Verilog-AMS models can be used with SPICE and VHDL-AMS models. Users can select Verilog-AMS files as a source directly in the Model and Symbol Wizard.
EDM Integration Enhancements
Improved Simulation Data Structure
The simulation database has been restructured to allow multiple users to access and sync data within the same folder. This change supports parallel workflows and helps teams avoid conflicts during simulation setup.
Download Shared Files Without Full Checkout
Users can now download individual files without checking out the full simulation folder. This applies to commonly shared files such as stackup files, .bud, .ddr, .sws, and .ref files. With the right permissions, these files can be exported and shared directly with colleagues, saving time and effort.
Run Simulations Without Layout Check-In
Designers working on PCB layouts no longer need to check in their design to run simulations. HyperLynx now supports simulations on the latest saved layout version, helping teams avoid workflow interruptions and keep layout and simulation work in sync.
Enhanced PCB Version Metadata
A new column and property field display the PCB version metadata used in each simulation. This makes it easier to track which version of the PCB layout was used, improving traceability and project management.
Support for ODM Files
HyperLynx now supports ODM files with EDM-specific data types. This enhancement improves performance and reduces loading times when working with large or complex designs.
Better Stability and Sync Performance
General improvements have been made to EDM stability and syncing, providing a smoother experience when managing simulation data across teams and repositories.
Ready to Try HyperLynx 2504?
We invite you to request a free trial license through Sintecs, the official HyperLynx distributor. Our team will help you get started with the tools best suited for your design challenges.
Contact Sintecs today to request your trial and take the next step toward faster, more reliable electronics development.
