Understanding (LP) DDR4 & DDR5: U2U Presentation by Hans Klos

We’re excited to share an insightful presentation from the Siemens EDA U2U 2024 conference, delivered by Hans Klos, titled “Understanding DDR5 and LPDDR5: Key Signal Integrity (SI) and Power Integrity (PI) Challenges” (click here to download the PDF slide deck). If you work in high-speed memory design, this is a must-watch session packed with valuable technical knowledge.

In this presentation, Hans Klos delves into:

Key Topics Covered:

• Signal Integrity Challenges: DDR5’s increased data rates bring new complexities like shorter bit periods and faster rise times. Hans explores the critical aspects of insertion loss, return loss, crosstalk, and timing margin, emphasizing the importance of power-aware simulations.
• Power Integrity for DDR5/LPDDR5: With DDR5/LPDDR5’s lower supply and I/O voltages, power supply impedance and noise margins are becoming increasingly sensitive. The presentation addresses the new JEDEC standards and the role of AC decoupling simulation in optimizing Power Distribution Networks (PDN).
• Simulation Models and PCB Design: Hans highlights the role of accurate IBIS-AMI models, package simulations, and the challenges posed by PCB materials such as insertion loss and dielectric constant variations.
• Key Design Recommendations: Learn about routing topology, managing stub lengths, and the essential role of simulation in validating layout decisions for high-performance designs.

Why You Should Watch:

If you’re involved in high-speed memory designs, particularly for DDR5 and LPDDR5, this session provides deep technical insights that will help you overcome the key SI and PI challenges you’re likely to encounter. Hans offers actionable advice on stack-up design, layout strategies, and power-aware simulations that will be crucial for achieving optimal performance.

At Sintecs, we specialize in providing advanced Signal Integrity (SI) and Power Integrity (PI) engineering solutions tailored to meet the demands of high-speed designs like DDR5 and LPDDR5. Our team of experts offers comprehensive support, from pre-layout simulations to final system verification, ensuring your designs are optimized for performance and reliability. Additionally, we provide IBIS Development Studio to our users for free.

Reach out to Sintecs for more information and take advantage of these resources to enhance your engineering projects.